Phase-locked loop (PLL) circuits are commonly used in frequency synthesizers found in analog and digital communications systems. A PLL typically generates an output frequency which is different from a reference frequency. FIG. 1 illustrates a basic PLL circuit 10.
In a communications system incorporating PLL circuit 10, a reference frequency of, for example, 19.68 MHz is generated within the system, and it is desired to synthesize a frequency of, for example, 9.8304 MHz. The ratio of this input frequency and output frequency is equal to 2050 divided by 1024, which is approximately 2.00195. This ratio is achieved by using dividers 12 and 14 in FIG. 1 connected to receive the signals on lines 16 and 18, respectively. These divided signals are applied to the input terminals of a phase detector 20, which compares the two signals and outputs a signal related to the difference in phase of the two input signals. There are many types of phase detectors. One type of phase detector 20 generates a positive or negative charge pulse, depending on whether the phase of the divided reference frequency leads or lags the divided output frequency. These charge pulses are accumulated to create a voltage whose amplitude is proportional to the phase difference between the two signals. Such a phase detector thus acts as a charge pump. In another embodiment, phase detector 20 outputs pulses whose widths depend on the phase difference between the two input signals. The DC component is thus proportional to the phase difference between the two input signals.
The output of phase detector 20 in response to a phase lag of the divided reference frequency causes a voltage controlled oscillator (VCO) 22 to decrease its output frequency until the signals at the inputs of phase detector 20 are matched in phase. Conversely, a phase lead of the divided reference frequency causes a signal to be generated by phase detector 20 to cause VCO 22 to increase its output frequency until the signals at the inputs of phase detector 20 are matched in phase.
A lowpass filter 26 connected between phase detector 20 and VCO 22 smooths the output of phase detector 20 into a substantially DC signal for controlling VCO 22. Filter 26 also smooths the response of the PLL to prevent overshoot or oscillations. Phase detector 20, filter 26, and VCO 22 may be any conventional circuits. VCO 22 may be an analog or digital circuit, including a digital delay line.
One problem with the PLL of FIG. 1 is that, since the divided reference frequency at the input of phase detector 20 is 19.68 MHz/2050, having a period of 104.2 microseconds, there is a relatively long time between updates. Hence, relatively large output frequency drifts may occur between the updates, and a robust low frequency filter 26 is required to filter these potentially large excursions between updates. Robust low frequency filters require large capacitive components which are not integratable on a single chip.
FIG. 2 illustrates another type of PLL 32. The scheme of FIG. 2 removes one of every 1025 pulses of the reference frequency on line 34, then divides the resulting frequency by 1/2, so that the frequency applied to phase detector 20 on line 41 is equal to the desired output frequency of 9.8304 MHz on line 36. Instead of using a frequency divider, a pulse swallower 38 is used in conjunction with a divide-by-2 divider 40. The pulse swallower, in the particular case of FIG. 2, counts 1024 pulses and simply deletes the 1025th pulse. This effectively results in an average frequency of 19.68 MHz times 1024/1025 being output by pulse swallower 38.
The disadvantage of the scheme in FIG. 2 is that pulse swallower 38 creates a very large phase error at the 1025th pulse. This large phase error requires a robust low pass filter 42, requiring filter 42 to incorporate large capacitors which could not be implemented on an integrated circuit.
What is needed is a PLL circuit which does not suffer from the drawbacks of PLL circuits described above.